Array substrate for flat display device

ABSTRACT

An object of this array substrate for a flat display device is to eliminate display unevenness caused by the inequality of parasitic capacitances of switches of signal line switch circuits. Electrode patterns (P) which connects the gate electrodes of the switches (ASW) to any one of a plurality of switch control signal lines (ASWL 1  and ASWL 2 ) are formed so as to each two-dimensionally overlap all of the switch control signal lines ASWL and to have substantially identical shapes, thus equalizing the areas of the electrode patterns (P).

TECHNICAL FIELD

The present invention relates to an array substrate for a flat displaydevice. Specifically, the present invention relates to an electrodestructure of a signal line drive circuit.

BACKGROUND ART

In word processors, personal computers, portable TVs, and the like, thinand light flat display devices are widely used. In particular, liquidcrystal display devices are being actively developed because of the easeof reducing the thickness, weight, and power consumption thereof. Oneshaving high resolutions and large screen sizes have become available atrelatively low prices.

Among liquid crystal display devices, active matrix liquid crystaldisplay devices in which a thin film transistor (TFT) is placed as aswitching element in the vicinity of each of the intersections betweensignal lines and scan lines are considered to become mainstream in thefuture because of their excellent color appearance and weak afterglow.

In a liquid crystal display device using amorphous silicon TFTs, tapecarrier packages (TCPs) are used which are constructed by mountingsignal line drive ICs and scan line drive ICs on flexible wiring boards.By electrically connecting these TCPs to external connection terminalsof an array substrate, the signal line drive ICs and the scan line driveICs are electrically connected to pixel electrodes on the arraysubstrate, and pixel transistors are driven.

In this liquid crystal display device using amorphous silicon TFTs, alarge number of interconnections are necessary for supplying picturesignals from the TCPs to signal lines on an array substrate.Accordingly, in the case where the definition of pixels is improved, itis difficult to ensure a sufficient pitch between the interconnections.In this connection, for example, a technology described in JapaneseUnexamined Patent Publication No. 2001-109435 has been known. In thistechnology, a signal line drive circuit is constructed using a switchcircuit formed on an array substrate and signal line drive ICs mountedon TCPs. Each interconnection extended from the signal line drive ICs isconnected to two adjacent signal lines one after another within onehorizontal scan period using a pair of switches in the switch circuit,thus supplying the two signal lines with picture signals by timedivision.

In the above-described switch circuit, both of the source electrodes ofa pair of switches are connected to a common interconnection extendedfrom a signal line drive IC, the drain electrodes thereof arerespectively connected to adjacent different signal lines, and the gateelectrodes thereof are respectively connected to different switchcontrol signal lines. Further, a signal line connected to theinterconnection is switched according to switch control signals suppliedto the gate electrodes.

The gate electrodes of the switches and the switch control signal linesare connected by electrode patterns. The electrode patterns are laid outin accordance with the positions of contact holes connected to theswitch control signal lines. Accordingly, when attention is focused on apair of switches, the left and right switches have different lengthsfrom the switch control signal lines to the respective gate electrodes,and a difference occurs in the areas of the electrode patterns. Thus,the parasitic capacitances become unequal. Consequently, there is adifference between the times required to charge adjacent pixels withdata signals. In some cases, display unevenness is caused.

Further, in the above-described layout, electrode patterns havingdifferent lengths are alternately arranged in a continuous manner.Accordingly, differences in length are difficult to find, and there isthe problem that pattern abnormalities are difficult to find by visualinspection.

Furthermore, in the case where the connections between the electrodepatterns and the switch control signal lines are changed, not only acontact hole formation layer but also the electrode patterns need to bechanged. Along with this, a plurality of masks needs to be changed.Accordingly, there is the problem that a design change is expensive andthat it is difficult to flexibly cope with a change to other drivesystem having a different connection form.

DISCLOSURE OF THE INVENTION

An array substrate for a flat display device according to a first aspectof the present invention is characterized by including: a display unitin which a pixel is placed at each of intersections between a pluralityof signal lines and a plurality of scan lines, which signal and scanlines are routed in the form of a matrix; a plurality of output linesconfigured to output data signals to the signal lines, respectively; aplurality of switches placed between the output lines and the signallines to connect each output line to n signal lines (n is an integerequal to or greater than two) one after another within one horizontalperiod; n switch control signal lines configured to supply controlelectrodes of the switches with control signals for controlling on andoff states thereof; and a plurality of electrode patterns configured toconnect the control electrode of each switch to any one of the n switchcontrol signal lines. The array substrate is further characterized inthat the electrode patterns each two-dimensionally overlap all of theswitch control signal lines and have substantially identical shapes.

In this aspect, the shapes of the electrode patterns connecting thecontrol electrodes of the switches and the switch control signal linesare shapes which two-dimensionally overlap all of the switch controlsignal lines, and are substantially identical shapes. This equalizes theparasitic capacitances of all switches. Accordingly, it is possible toeliminate display unevenness caused by the inequality of parasiticcapacitances and to obtain favorable display characteristics. Further,differences in the lengths of the electrode patterns are easy to find,and pattern abnormalities can be easily found by visual inspection.Thus, process yield can be improved by the early detection of patternabnormalities.

A second aspect of the present invention is the above-described arraysubstrate for a flat display device which is characterized in that theelectrode patterns and the switch control signal lines are stacked withan insulating layer interposed therebetween, and are electricallyconnected to each other by contact holes formed in the insulating layer.

In this aspect, the electrode patterns and the switch control signallines are electrically connected by the contact holes. This makes itpossible to change the connecting positions between the electrodepatterns and the switch control signal lines only by changing a contacthole formation layer. Thus, the cost of a design change can be reduced.Further, it is possible to flexibly cope with a change to other drivesystem having a different connection form.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the configuration of a flat displaydevice of one embodiment.

FIG. 2 is a circuit diagram showing the configuration of a signal lineswitch circuit shown in FIG. 1.

FIG. 3 is a circuit diagram showing the configuration of a signal lineswitch circuit of a comparative example.

BEST MODES FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be describedwith reference to the drawings.

As shown in the circuit diagram of FIG. 1, in a flat display device ofthis embodiment, scan lines G1 to Gm (hereinafter referred to as “scanlines G” as appropriate) and signal lines S1 to Sn (hereinafter referredto as “signal lines S” as appropriate) are routed in the form of amatrix in a display unit 101 on an array substrate 100. A pixel isplaced at each of the intersections between the scan lines G and thesignal lines S. Each pixel includes a pixel transistor 102, a pixelelectrode 103, and an auxiliary capacitor 106. A common electrode 104placed to face the pixel electrodes 103 is formed on a counter substrate(not shown). A liquid crystal layer 105 is held between the pixelelectrodes 103 and the common electrode 104. The auxiliary capacitor 106is connected in parallel to the pixel electrode 103. A predeterminedauxiliary capacitor voltage is supplied to the auxiliary capacitor 106through an auxiliary capacitor line (not shown).

In an upper edge portion of the display unit 101, signal line drivecircuit units 111 are placed. To left and right edge portions of thedisplay unit 101, scan line drive circuits 115 are connected. Thedisplay unit 101 is divided into four blocks. The signal lines S aresegmented into a predetermined number of signal line groups in eachblock. Data signals are respectively supplied to the signal lines fromthe signal line drive circuit units 111 which have identicalconfigurations and which are placed to correspond to the respectiveblocks.

The signal line drive circuit units 111 include four signal line driveICs 112 and four signal line switch circuits 113. The signal line driveICs 112 output data signals to output lines described later, and outputvarious kinds of signals. The signal line switch circuits 113 outputdata signals supplied from the signal line drive IC 112, to all of thesignal lines of each signal line group, one signal line group afteranother within one horizontal scan period. The signal line drive ICs 112are mounted on TCPs 120-1 to 120-4. The signal line switch circuits 113are formed on the array substrate 100. One side edges of the TCPs 120-1to 120-4 are connected to external connection terminals formed along oneedge of the array substrate 100, and the opposite side edges thereof areconnected to an external drive circuit 200.

The scan line drive circuits 115 sequentially output, to the scan linesG1 to Gm, scan signals for bringing the pixel transistors 102 intoconduction and writing data signals into the pixel electrodes 103 fromthe signal lines S. The scan line drive circuits 115 are mounted on thearray substrate 100.

On the external drive circuit 200, a control IC 201, and a power supplycircuit, an interface circuit, and the like (not shown) are mounted.

The control IC 201 sorts data signals inputted from the outside in theorder in which the data signals are outputted to the signal lines, andoutputs the data signals. Additionally, the control IC 201 generatesvarious kinds of timing signals, a clock signal, a control signal, andthe like based on a reference clock signal inputted in synchronizationwith the data signals, and outputs them. More specifically, the controlIC 201 supplies the scan line drive circuits 115 with a start signal andthe clock signal, and supplies the signal line drive ICs 112 with sorteddata signals, a register control signal, the clock signal, a loadsignal, and the like.

Further, the control IC 201 includes the function of controlling controlsignals (switch control signals) for controlling the on and off statesof switches in this embodiment, and supplies the control signals to thesignal line switch circuits 113.

The liquid crystal display device including the above-described arraysubstrate 100 is constructed by placing the array substrate 100 and acounter substrate (not shown) so that they face each other apredetermined distance apart, bonding the perimeters thereof togetherwith a sealant, and filling the liquid crystal layer 105 into the spacebetween the array substrate 100 and the counter substrate.

As shown in the circuit diagram of FIG. 2, in the signal line switchcircuits 113, switches ASW1, ASW2, ASW3, ASW4, . . . , ASWn-1, and ASWn(hereinafter referred to as “ASWs” or “switches ASW” as appropriate) areplaced. Here, as one example, the switches ASW are switches having MOSstructures. The signal lines S1, S2, S3, S4, . . . , Sn-1, and Sn areconnected to the drain electrodes of the switches ASW, respectively.From the signal line drive ICs 112, output lines D1, D2, . . . , and Dx(hereinafter referred to as “output lines D” as appropriate) are routed.

Using the switches, each output line D is connected to n signal lines S(n is an integer equal to or greater than two) one after another withinone horizontal period. In this embodiment, as one example, the value ofn is set to two. Each output line D is connected to both of the sourceelectrodes of two adjacent ASWs.

That is, for each output line D, two ASWs are arranged in a pair. Thesource electrodes of the two ASWs are connected to one common outputline D. Further, the drain electrodes thereof are connected to differentcorresponding signal lines S, respectively.

From the signal line drive ICs 112 to the signal line switch circuits113, n switch control signal lines ASWL are routed. Here, as oneexample, the value of n is two. Accordingly, the signal line switchcircuits 113 have two switch control signal lines ASWL1 and ASWL2(hereinafter referred to as “ASWLs” or “switch control signal linesASWL” as appropriate).

Each of the switch control signal lines ASWL1 and ASWL2 is connected toalternate ones of the control electrodes (gate electrodes) of theswitches ASW1, ASW2, ASW3, ASW4, . . . , ASWn-1, and ASWn.

The ASWs in this embodiment are, for example, n-type TFTs. In this case,for example, when a switch control signal ASW1U at a high potential issupplied to the switch control signal line ASWL1, the switches ASW2,ASW4, . . . , and ASWn are turned on, whereby data signals outputted tothe output lines D1, D2, . . . , and Dx are supplied to the signal linesS2, S4, . . . , and Sn.

On the other hand, when a switch control signal ASW2U at a highpotential is supplied to the switch control signal line ASWL2, theswitches ASW1, ASW3, . . . , and ASWn-1 are turned on, whereby datasignals outputted to the output lines D1, D2, . . . , and Dx aresupplied to the signal lines S1, S3, . . . , and Sn-1.

In this embodiment, two data write periods are provided in onehorizontal scan period. For example, in the first data write period, aswitch control signal ASW1U at a high potential is supplied to theswitch control signal line ASWL1, and, in the second data write period,a switch control signal ASW2U at a high potential is supplied to theswitch control signal line ASWL2. Thus, switching is performed betweenthe signal lines S2, S4, . . . , and Sn and the signal lines S1, S3, . .. , and Sn-1 within one horizontal scan period. This makes it possibleto write data signals for one horizontal line into pixel electrodes.Such a drive system is called a signal line selection method. Theadoption of a signal line selection method can reduce the number ofrouted output lines D connected to the array substrate 100 from theoutside.

In FIG. 2, the gate electrodes of the switches ASW1, ASW2, ASW3, ASW4, .. . , ASWn-1, and ASWn are connected to the switch control signal linesASWL1 and ASWL2 by electrode patterns P1, P2, P3, P4, . . . , Pn-1, andPn (hereinafter referred to as “electrode patterns P” as appropriate)made of metal.

The electrode patterns P are formed so as to each two-dimensionallyoverlap all switch control signal lines ASWL and have substantiallyidentical shapes. Here, since the value of n is two, alternate ones ofthe electrode patterns P extended from the gate electrodes of theswitches AWS are connected to the same switch control signal line ASWL.

The electrode patterns P1, P2, P3, P4, . . . , Pn-1, and Pn areelectrically connected to the switch control signal lines ASWL1 andASWL2 by contact holes C1, C2, C3, C4, . . . , Cn-1, and Cn (hereinafterreferred to as contact holes C as appropriate). The electrode patterns Pand the switch control signal lines ASWL are stacked with an insulatinglayer (not shown) interposed therebetween. The contact holes C formed inthis insulating layer allow each electrode pattern P to have electricalcontinuity only with one predetermined switch control signal line ASWL.

In the above-described configuration, all electrode patterns Ptwo-dimensionally overlap the switch control signal lines ASWL1 andASWL2 and are formed in patterns of substantially identical shapes.Accordingly, the areas of the electrode patterns P are approximatelyidentical, and the parasitic capacitances of the switches ASW are alsoapproximately equal.

Subsequently, the electrode configuration of a signal line switchcircuit of a comparative example will be described. As shown in FIG. 3,in the signal line switch circuit of the comparative example, thelengths of electrode patterns from switch control signal lines ASWL1 andASWL2 to the gate electrodes of left and right switches ASW in a pairare different between the left and right. Accordingly, a difference alsooccurs in the areas of the electrode patterns. As a result, theparasitic capacitances of the left and right switches ASW are unequal.Incidentally, in FIG. 3, components equivalent to those in FIG. 1 aredenoted by the same reference numerals as those in FIG. 1.

On the other hand, in the electrode configuration of this embodiment,all ASWs have approximately equal parasitic capacitances. Accordingly,the times required to charge adjacent pixels with data signals are alsoapproximately equal. Thus, display unevenness is eliminated, andfavorable display characteristics can be obtained.

Further, in the electrode configuration of this embodiment, as shown inFIG. 2, electrode patterns having identical shapes are continuouslyplaced. Accordingly, differences in length are easy to find, and patternabnormalities can be easily found by visual inspection. This makes itpossible to find pattern abnormalities early. Thus, process yield can beimproved.

Furthermore, the electrical connections between the electrode patterns Pand the switch control signal lines ASWL can be appropriately set bychanging the positions where the contact holes are formed. Accordingly,in the case where the connections between the electrode patterns P andthe switch control signal lines ASWL are changed, it is only necessaryto change a contact hole formation layer, and the patterns of metal donot need to be changed. Thus, there is no need to change a plurality ofmasks, and an increase in the cost of a design change can be reduced.Additionally, it is possible to flexibly cope with a change to otherdrive system having a different connection form and to increase theflexibility of circuit design.

In this embodiment, a description has been given of a configuration inwhich each output line D extended from the signal line drive ICs 112 isbranched to a pair of switches ASW to be connected to two signal lines.However, the present invention is not limited to this. It is possible toadopt a configuration in which each output line D is branched to n ASWs(n is an integer equal to or greater than two) to be connected to nsignal lines.

Moreover, in this embodiment, a description has been given of an examplein which the display unit 101 is divided into four blocks and in which asignal line drive IC 112 and a signal line switch circuit 113 arearranged for each block. However, the present invention is not limitedto this. For example, the number of blocks into which the display unit101 is divided may be larger, or the display unit 101 may be a singleblock without division.

1. An array substrate for a flat display device comprising: a displayunit in which a pixel is placed at each of intersections between aplurality of signal lines and a plurality of scan lines, the signal andscan lines being routed in the form of a matrix; a plurality of outputlines configured to output data signals to the signal lines,respectively; a plurality of switches placed between the output linesand the signal lines to connect each output line to n signal lines (n isan integer equal to or greater than two) one after another within onehorizontal period; n switch control signal lines configured to supplycontrol electrodes of the switches with control signals for controllingon and off states thereof; and a plurality of electrode patternsconfigured to connect the control electrode of each switch to any one ofthe n switch control signal lines, wherein all of the electrode patternshave substantially identical shapes and two-dimensionally overlap all ofthe switch control signal lines, and areas of all the electrode patternsare substantially identical.
 2. The array substrate according to claim1, wherein the electrode patterns and the switch control signal linesare stacked with an insulating layer interposed therebetween, and areelectrically connected to each other by contact holes formed in theinsulating layer.